Photonic interconnect for wafer-scale chips

November 02, 2020 //By Rich Pell
Photonic interconnect fabric supports future computing, AI
A wafer-scale, programmable photonic interconnect from LightMatter in the US connects arrays of heterogeneous chips

A fully-reconfigurable photonic connection topology between chips can reduce the cost and complexity of building heterogeneous computing systems says US startup Lightmatter. The Lightmatter Passage fabric enables forty switchable integrated photonic lanes can fit into the same space as one optical fibre.

The result is higher bandwidth communication at lower energy and without the cost of fibre-to-chip packaging. This provides a proven path to chip-to-chip communications with 100-Tbps bandwidth - 100x that of currently available state-of-the-art photonic interconnect solutions.

"Lightmatter is leading a necessary paradigm shift in computer architecture needed to power the next giant leaps in compute technology, while also reducing the negative impact on our planet of rapidly-growing state of the art, yet inefficient, compute and communications solutions,” said Nick Harris, co-founder and CEO at Lightmatter. "Modern compute workloads call for system-level performance. With Passage, we've created a photonic rack-on-chip solution capable of supporting the future of computing by enabling ultra-high bandwidth interconnection between different kinds of chips, and simultaneously reducing cost, complexity, and energy consumption."Planned to be the first in a multi-year roadmap of interconnects with increasing performance, Passage enables 1-Tbps dynamically reconfigurable interconnect across an array of 48 chips spanning 8 x 8 inches, with a maximum communication latency of 5 nanoseconds.

Passage follows the introduction of an artificial intelligence (AI) photonic computer chip: a general-purpose AI inference accelerator that uses light to compute and transport data—reducing heat & energy consumption and increasing computational performance by orders of magnitude. Passage, says the company, provides the capability to integrate this chip with a heterogeneous selection of other chips to enable a single wafer-scale, high-speed compute system.

The system directly addresses the urgent need for faster and more energy efficient (super)computers, capable of supporting next-generation AI inference and training workloads. The latest-and-greatest AI models require the capability of entire datacenters to train effectively, meaning single chip systems are no longer able to address the compute needs of current and future AI problems. Photonic-enabled systems,

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