Based on a highly optimized new architecture, the Achronix Speedster7t family is said to deliver ASIC-like performance with the adaptability and enhanced functionality of FPGAs. The 2D network-on-chip (NoC), and a high-density array of new machine learning processors (MLPs) blocks optimised for high-bandwidth and AI/ML workloads effectively blend FPGA programmability with ASIC routing structures and compute engines.
Manufactured on TSMC’s 7nm FinFET process, Speedster7t devices are designed to accept massive amounts of data from multiple high-speed sources, distribute that data to programmable on-chip algorithmic and processing units, and then deliver those results with the lowest possible latency. They include high-bandwidth GDDR6 interfaces, 400G Ethernet ports, and PCI Express Gen5 — all interconnected to deliver ASIC-level bandwidth while retaining the full programmability of FPGAs.
At the heart of Speedster7t FPGAs are a massively parallel array of programmable compute elements within the highly configurable machine learning processors (MLPs). The MLPs are compute-intensive blocks that support integer formats from 4 to 24 bits and efficient floating-point modes including direct support for TensorFlow’s 16-bit format as well as the supercharged block floating-point format that doubles the compute engines per MLP.
The MLPs are tightly coupled with embedded memory blocks, eliminating the traditional delays associated with FPGA routing to ensure that data is delivered to the MLPs at the maximum performance of 750 MHz.
Speedster7t devices are the only FPGAs with support for GDDR6 memories, the highest bandwidth external memory devices. With each of the GDDR6 memory controllers capable of supporting 512 Gbps of bandwidth, the up to 8 GDDR6 controllers in a Speedster7t device can support an aggregate GDDR6 bandwidth of 4 Tbps, delivering the equivalent memory bandwidth of an HBM-based FPGA at a fraction of the cost.
The Speedster7t FPGA devices range from 363K to 2.6M 6-input LUTs. The first devices and development boards for evaluation will be available in Q4 2019. The ACE design tools that support all of Achronix’s products including