The first-generation chip family, named Rhea, will include Arm ZEUS architecture general purpose cores and prototypes of high energy-efficient accelerator tiles: RISC-V based (EPAC), Multi-Purpose Processing Array (MPPA), embedded FPGA (eFPGA) and cryptography HW engine. The consortium anticipates that the first Rhea chips will be fabricated in N6 technology aiming at the highest processing capabilities and energy efficiency.
The Rhea chips are to be integrated into test platforms, both in workstations and supercomputers in order to validate the hardware units, develop the necessary software interfaces, and run applications. Rhea aims to be the European processor for several experimental platforms towards exascale HPC and future automotive designs.
Members of the project have also defined a common approach: the EPI Common Platform (CP), including a global architecture specification (hardware and software), a common design methodology, and a global approach for power management and security. The aim of defining the EPI CP is to harmonize the heterogeneous computing environment. The Common Platform in the Rhea family of processors will be organized around a 2D-mesh Network-on-Chip (NoC) connecting computing tiles based on general purpose Arm cores with previously mentioned accelerator tiles.