Driver monitoring ASIC adds AI and DDR3 memory for Euro NCAP

January 04, 2021 //By Nick Flaherty
Driver monitoring ASIC adds AI and DDR3 memory for Euro NCAP
The 1W OAX8000 stacked die system-in-package is aimed at obligatory entry level driver monitoring systems for processing eye gaze and eye tracking algorithms says Omnivision with a 1s boot time.

OmniVision Technologies has launched an entry level AI stacked die system-in-package for driver monitoring systems (DMS) and FaceID security based around four ARM Cortex A5 cores.

The OAX8000 uses a stacked-die architecture to provide the industry’s only DMS processor with on-chip DDR3 SDRAM memory (1GB). This is also the only dedicated DMS processor to integrate a neural processing unit (NPU) and image signal processor (ISP), which provides dedicated processing speeds up to 1.1 trillion operations per second for eye gaze and eye tracking algorithms.

The fast processing speeds with 1K MAC of convolutional neural network (CNN) acceleration, along with integrated SDRAM, enable the lowest power consumption available for DMS systems— at 1W. The system-in-package integration into a BGA196 package also reduces the board area for the engine control unit (ECU).

The market for DMS driver monitoring is expected to see a 56 percent annual growth between 2020 and 2025 says Yole Développement, driven by the European Union’s Euro NCAP requirement that all new cars sold in the region have a DMS camera by 2022.

“Most DMS processors on the market today are not dedicated to this application, requiring added circuitry to perform other system functions that consumes more power, occupies more board space and doesn’t allow room for on-chip SDRAM,” said Brian Pluckebaum, automotive product marketing manager at OmniVision. “By focusing the design of our OAX8000 ASIC on entry-level DMS, we were able to create the automotive industry’s most optimized solution.”

The OAX8000’s on-chip NPU is developed in-house and supports the popular TensorFlow, Caffe, MXNet and ONNX tool chains. The quad Arm Cortex A5 CPU cores have Neon signal procesing extensions for accelerated video encoding/decoding and on-chip video analytics algorithms, along with hardware for image processing, video encoding and RGB/IR processing. The high dynamic range (HDR) processing capability allows the ASIC to accept input from RBG/IR image sensors and support high quality output, for videos taken during the day or at night, in conditions with widely contrasting bright and dark

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