proFPGA prototyping systems handle complex ASIC and SoC designs of up to 2 Billion ASIC gates and give design and verification engineers unprecedented opportunities for high-speed verification and bug hunting to shorten the time to market by eliminating costly re-spins and providing early prototypes for software development and/or end customers.
When using FPGA-based prototyping design bring up and partitioning are the most complex, time-consuming and challenging tasks and this gets even worse because of fast-growing design sizes and required numbers of FPGAs. Typically, manual partitioning and design implementation for multi-FPGA platforms takes several days, weeks or even months without any tool support or guidance.
Instead of offering a completely automated "push button" flow with limited control, proFPGA Cut guides the user through the partitioning process step by step from importing RTL to exporting it for synthesis and place & route. This way, users still have full control over their design to allow a maximum design speed and the tool supports them to shorten this usually time consuming and complex process. proFPGA Cut offers the insertion of pin multiplexing IPs, logic optimization, constraints setting, conversion of multi-point interconnections into point-to-point interconnections, semi-automated movement of instances/ nets, etc.
Thanks to an easy-to-use GUI, all steps in the tool flow and their availability are visualized, giving users a structured overview and workflow. A tree structure is used to display the design hierarchy and all external access ports (IOs) are shown and can be mapped into physical pins. Furthermore, the proFPGA Cut GUI displays all design interconnections between FPGAs and how they are physically mapped. The proFPGA Cut tool works on RTL and not on netlist level, making it independent of the FPGA platform.
Pro Design - www.proFPGA.com