ARM splits its Neoverse datacentre server chip designs

September 22, 2020 //By Nick Flaherty
ARM has split its Neoverse datacentre processors into separate lines for high performance and for scaling in existing racks and for edge AI.
ARM has split its Neoverse datacentre processors into separate lines for high performance vector processing and for scaling in existing racks and for edge AI.

The company launched its first Neoverse core, the N1, last year, which in a 7nm process saw a 60 percent performance boost over the previous Cortex-A72. The N1 has been used for multiple datacentre server chip designs, including Amazon’s Graviton 2. Altran and NXP have also used for core for the next generation Layerscape 5G network processors.

Now it is splitting the line with the successor N2, codenamed Perseus, and the V1, codenamed Zeus, the company’s first scalar vector processor for high performance server designs. This has even more significance with the proposed acquisition of ARM by Nvidia with a focus on the data centre alongside GPU cores.

“The emergence of ARM in the data centre is powered by many factors, all built on performance,” said Chris Bergey, general manager of the ARM infrastructure business. “We started with a power performance message and this didn’t resonate – we had a performance gap to close.”

“The N2 Perseus we expect to offer 40 percent higher performance over N1 with the same area and power efficiency for scale out cloud, smartNIC and edge devices,” he said.

The V series will be optimised for higher performance than N2, with larger buffers, cache, windows and queues that allow a single thread to execute faster. It will also support two 256bit vector instructions for high performance computing (HPC), cloud computing and AI. SiPearl and the European ExaScale project are planning to use the cores in high performance system-on-chip designs for supercomputers.

This will support scalar vector extensions (SVE) with full control over voltage and frequency transitions when moving between linear and vector instructions. “This has run at full frequency with SVE code and transition seamlessly between memory register widths for helper code,” said Bergey.

The split gives developers a choice, says Berger. With the N2, a 42U rack in a data centre with a 25kW power supply can run significantly more thread throughput and the cloud provider


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